VLSI USING VHDL/VERILOG

DOMAIN: COMMUNICATION

1. VLSI01 RTL DESIGN AND SIMULATION OF MICRO
CONTROLLER IN HDL

2. VLSI02 RTL DESIGN AND SIMULATION OF 8 – BIT
CPU IN HDL

3. VLSI03 DESIGN AND IMPLEMENTATION OF
FLOATING POINT ADDER UNIT IN VHDL

4. VLSI04 RTL DESIGN AND COMPARISON FOR
VARIOUS MULTIPLIER ARCHITECTURES

5. VLSI05 HDL IMPLEMENTATION OF ERROR
DETECTION AND CORRECTION CIRCUIT

6. VLSI06 DESIGN AND IMPLEMENTATION OF HIGH
SPEED MATRIX MULTIPLIER BASED ON
WORD-WIDTH DECOMPOSITION

7. VLSI07 RTL SIMULATION OF QPSK MODEM

8. VLSI08 DESIGN AND IMPLEMENTATION OF 64 POINT
FFT / IFFT FOR IEEE 802.11A

9. VLSI09 DESIGN AND IMPLEMENTATION OF DIRECT
DIGITAL SYNTHESIZERS FOR WIRELESS
APPLICATIONS

10. VLSI10 DESIGN AND IMPLEMENTATION OF DIGITAL
DOWN CONVERTER (DDC) =M.E

11. VLSI11 DESIGN AND IMPLEMENTATION OF DIGITAL
UP CONVERTER (DUC) =M.E

12. VLSI12 DESIGN AND IMPLEMENTATION OF SECOND
ORDER COSTOS LOOP FOR BPSK MODEM

13. VLSI13 DESIGN AND IMPLEMENTATION OF SECOND
ORDER COSTOS LOOP FOR QPSK MODEM

14. VLSI14 HDL IMPLEMENTATION OF LOGARITHMIC
AND ANTILOGARITHMIC CONVERTER

15. VLSI15 DESIGN AND IMPLEMENTATION OF LMS
ALGORITHM IN VHDL

16. VLSI16 IMPLEMENTATION OF DCT/IDCT ALGORITHM
IN VHDL

17. VLSI17 IMPLEMENTATION OF WAVELET BASED
COMPRESSION ALGORITHM IN HDL

18. VLSI18 DESIGN AND IMPLEMENTATION OF VLIW
STACK PROCESSOR IN HDL

19. VLSI19 DESIGN AND IMPLEMENTATION OF ALU IN
HDL

20. VLSI20 DESIGN AND IMPLEMENTATION OF DDFS IN
HDL

21. VLSI21 RTL SIMULATION OF VITERBI ALGORITHM

22. VLSI22 DESIGN AND IMPLEMENTATION OF REED
SOLOMON ENCODER IN HDL